Semiconductor integrated circuits typically are formed by metal-oxide semiconductor (MOS) or bipolar transistors that are integrated at a planar major surface of a silicon chip. Electrical interconnections between various transistors, as well as between certain transistors and access pins, have taken the form of two (or more) "levels" of interconnections, i.e., electrically connecting lines in the form of metallization strips running along two (or more) essentially planar surfaces that are oriented mutually parallel to, and are insulated from, both each other and the top planar surface of the chip by suitable insulating layers. Interconnection vias in the insulating layers are provided whenever needed for the desired circuit interconnections.
In a variety of integrated circuits, such as random access memories (RAMs) and logic circuits, the electrical circuit itself requires interconnections by means of a number of electrically conducting lines which conventionally are geometrically arranged in the form of an array of mutually parallel metallization strips. For example, in a dynamic RAM (DRAM) an array of parallel bit lines coupled to an array of memory cells (and addressed by an array of parallel word lines) can contain hundreds (or more) of parallel lines.
These bit lines, which typically comprise paired true and complement lines, can give rise to electrical cross-coupling or "cross-talk". For example, access to any given bit line may spuriously influence memory cells connected to adjacent bit lines. The term "pattern sensitivity" is applied to this undesirable phenomenon. The problem can arise in other interconnection arrays also, such as address busses and data busses wherein similarly paired, parallel disposed line conductors are employed. In any environment, such cross-talk can result in undesirable errors. Thus, although the concepts of the present invention are presented principally herein in connection with semiconductor memory arrays, they are equally applicable to any integrated circuit device employing a plurality of paired line conductors extending substantially parallel.
Architecture of semiconductor memories is roughly divided into two types, namely, open bit line architecture and folded bit line architecture. Both architecture types are well known in the art and detailed information on each type, along with numerous variations thereon, is readily available. FIG. 1 comprises a generalized diagram of an open bit line architecture, while FIG. 2 presents a closed bit line architecture. In an open bit line array, paired sets of bit lines (such as bit line 1 & bit line 1) are located on opposites sides of the respective sense amplifier. A significant advantage of this open structure is that a memory cell may be disposed at each word line--bit line crossing in the memory array. Unfortunately, the arrangement is also susceptible to differential noise being generated due to the physical separation of each true and complement pairing.
One solution to this differential noise has been to place the paired bit lines on the same side of the sense amplifier, thereby creating a folded bit line architecture. Differential noise problems are decreased in a folded bit line structure since both bit lines experience the same disturbance, thereby cancelling the effect of the disturbance. However, due to an ever decreasing spacing between bit lines, adjacent lines have now become differential noise sources. Noise can either be generated within a bit line pairing (intra-pair) or from one bit line pairing to another bit line pairing (inter-pair).
Several bit line "twisting" schemes have been proposed to reduce the effects of this bit line-to-bit line capacitance. For example, see Yoshihara et al., entitled "A Twisted Bit Line Technique For Multi-Mb DRAMS," IEEE International Solid-State Circuits Conference, pp. 238-239, February 1991; and Oowaki et al., entitled "A 33 ns 64 Mb DRAM," IEEE International Solid-State Circuits Conference, pp. 114-115, February 1991. These articles present several different line twist layouts for reducing intra-pair capacitive coupling and/or matching inter-pair capacitive couplings. Two of these layouts are discussed further herein with reference to FIGS. 3a-4b.
The present invention presents a line conductor layout and twist method which optimize density of the integrated circuit's interconnection array while avoiding intra-pair capacitive coupling and establishing matching of inter-pair capacitive couplings.